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? 1 ? e03736-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXD3059AR 120 pin lqfp (plastic) description the CXD3059AR is a digital signal processor lsi for cd players. this lsi incorporates a rf amplifier and digital servo, high & bass boost, 1-bit dac and analog low-pass filter. features ? all digital signal processing during playback is performed with a single chip highly integrated mounting possible due to a built-in rf amplifier rf block supports 4 speed playback cd rf system equalizer supports pickup built-in rf summing amplifier gain level switch te balance adjustment function digital signal processor (dsp) block supports cav (constant angular velocity) playback frame jitter free 0.5 to 4 speed continuous playback possible allows relative rotational velocity readout supports variable pitch playback the bit clock, which strobes the efm signal, is generated by the digital pll. efm data demodulation enhanced efm frame sync signal protection refined super strategy-based powerful error correction c1: double correction, c2: quadruple correction supported during 4 speed playback noise reduction during track jumps auto zero-cross mute subcode demodulation and subcode-q data error detection digital spindle servo 16-bit traverse counter asymmetry correction circuit cpu interface on serial bus error correction monitor signal, etc. output from cpu interface servo auto sequencer fine search performs track jumps with high accuracy digital audio interface outputs digital level meter, peak meter bilingual compatible vco control mode cd text data demodulation digital servo (dssp) block microcomputer software-based flexible servo control offset cancel function for servo error signal auto gain control function for servo loop e:f balance, focus bias adjustment functions surf jump function supporting micro two-axis tracking filter: 6 stages, focus filter: 5 stages digital filter, dac and analog low-pass filter blocks digital dynamic bass boost and high boost bass boost: 4th-order iir 24db/oct +10db/+14db/+18db/+22db high boost: second-order iir 12db/oct +4db/+6db/+8db/+10db independent turnover frequency selection possible bass b oost: 125hz/160hz/200hz high boost: 5khz/7khz cd digital signal processor with built-in rf amplifier and digital servo + digital high & bass boost digital dynamics (compressor) volume increased by +5db at low level 8 oversampling digital filter (attenuation: 61db, ripple within band: 0.0075db) digital signal output possible after boost serial data format selectable from (output) 20 bits/18 bits/16 bits (rearward truncation, msb first) digital attenuation: ? , ?60 to +6db, 2048 steps (linear) soft mute digital de-emphasis high-cut filter applications cd players structure silicon gate cmos ic absolute maximum ratings (ta = 25c) supply voltage 1 v dd , xv dd v ss ? 0.5 to +3.5 v input voltage 1 v i 1v ss ? 0.3 to v dd + 0.3 v output voltage 1 v o 1v ss ? 0.3 to v dd + 0.3 v supply voltage 2 iov dd 0 to 2, av dd 0 to 5 iov ss ? 0.5 to +4.5 v input voltage 2 v i 2iov ss ? 0.3 to iov dd + 0.3 v output voltage 2 v o 2iov ss ? 0.3 to iov dd + 0.3 v storage temperature tstg ?55 to +150 c supply voltage difference iov ss , av ss , xv ss ? v ss ?0.3 to +0.3 v xv dd ? v dd ?0.3 to +0.3 v iov dd , av dd , xv dd ? v dd ?0.3 to +0.3 v (iov dd , av dd , xv dd < 2.3v) recommended operating conditions supply voltage 1 v dd , xv dd 2.5 0.2 v supply voltage 2 iov dd 0 to 2, av dd 0 to 5 3.3 0.3 v operating temperature topr ?20 to +75 c i/o pin capacitance input capacitance c i 7 (max.) pf output capacitance c o 7 (max.) pf i/o capacitance c i/o 7 (max.) pf note) measurement conditions v dd = v i = 0v f m = 1mhz
? 2 ? CXD3059AR block diagram bass boost block cd signal prosessor block rfamp block servo block mirr dfct fok servo interface pwm generator dac servo dsp a/d converter te fe vc apc att eq amp cpu interface servo auto sequencer digital clv d/a interface efm demodulator sub code processor asymmetry corrector digital pll dc/dc convertor error corrector 32k ram lpf lpf clock generator digital out selector sstp cout atsk gfs xugf wfck emph wdck c2po scor sens clok xlat data exck sbso aout2 vrefr lmut rmut vrel aout1 emphi lrcki pcmdi bcki xtacn xtsl xtai bck pcmd lrck xrst tes1 test av dd 0 to 5 av ss 0 to 5 iov dd 0 to 2 iov ss 0 to 2 v dd v ss mirr dfct fok teo e f feo a b c vc sfdr srdr tfdr trdr ffdr frdr tei fei lock mdp xtao vctl vpco dout sqck sqso sclk sysm d pd pdsens ld rfaci bias asyi ddvrout ddvrsen ddcr asyo cltv fifo fili pco xpck rfdco ac_sum eq_in rfc rfaco sum
? 3 ? CXD3059AR pin configuration 36 35 34 31 32 33 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 40 39 38 37 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 97 96 95 94 91 92 93 99 98 73 74 81 82 83 84 75 76 77 78 88 87 86 85 79 80 89 90 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 rmut iov dd 0 nc av dd 2 aout2 vrefr av ss 2 av ss 1 vrefl aout1 av dd 1 xv dd xtai xtao xv ss nc iov ss 2 tes1 test dout iov dd 2 emphi emph v dd bck pcmd v ss lrck lrcki pcmdi lmut bcki nc nc xtsl ddcr iov ss 0 av ss 5 xtacn ddvrsen sqso ddvrout sqck av dd 5 sbso pco exck fili xrst filo sysm cltv data av ss 3 v ss vctl xlat vpco clok asyo v dd asyi sens bias sclk av dd 3 atsk rfaci wfck rfaco xugf av ss 4 xpck rfc gfs nc c2po pd scor ld v dd eq_in c4m ac_sum wdck pdsens cout rfdco nc av dd 4 mirr dfct fok v ss lock mdp sstp iov ss 1 sfdr srdr tfdr trdr ffdr frdr iov dd 1 av dd 0 av ss 0 nc e f tei teo fei feo vc a b c d nc
? 4 ? CXD3059AR pin description pin no. symbol i/o description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 mirr dfct fok v ss lock mdp sstp iov ss 1 sfdr srdr tfdr trdr ffdr frdr iov dd 1 av dd 0 av ss 0 nc e f tei teo fei feo vc a b c d nc av dd 4 rfdco pdsens ac_sum i/o i/o i/o ? i/o o i ? o o o o o o ? ? ? ? i i i o i o i/o i i i i ? ? i/o i o mirror signal input/output. defect signal input/output. focus ok signal input/output. internal digital gnd. gfs is sampled at 460hz; when gfs is high , this pin outputs a high signal. if gfs is low eight consecutive samples, this pin outputs low. or this pin inputs when lkin = "1". spindle motor servo control output. disk innermost detection signal input. i/o digital gnd. sled drive output. sled drive output. tracking drive output. tracking drive output. focus drive output. focus drive output. i/o digital power supply. analog power supply. analog gnd. e signal input. f signal input. tracking error signal input to dssp block. tracking error signal output from rf amplifier block. focus error signal input to dssp block. focus error signal output from rf amplifier block. center voltage output from rf amplifier block. center voltage input to dssp block by command switch. a signal input. b signal input. c signal input. d signal input. analog power supply. rfdc signal output. rfdc signal input to dssp block by command switch. reference voltage pin for pd. rfac summing amplifier output. power supply 1, 0 1, 0 1, 0 ? 1, 0 1, z, 0 ? 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 ? ? ? ? ? ? analog digital i/o = 3.3v internal = 2.5v a/d 3.3v ? rfamp 3.3v
? 5 ? CXD3059AR pin no. symbol i/o description 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 eq_in ld pd nc rfc av ss 4 rfaco rfaci av dd 3 bias asyi asyo vpco vctl av ss 3 cltv filo fili pco av dd 5 ddvrout ddvrsen av ss 5 ddcr nc bcki pcmdi lrckl lrck v ss pcmd bck v dd emph emphi i o i ? i ? o i ? i i o o i ? i o i o ? o i ? i ? i i i o ? o o ? o i equalizer circuit input. apc amplifier output. apc amplifier input. equalizer cut-off frequency adjustment pin. analog gnd. rfac signal output. rfac signal input or efm signal input. analog power supply. asymmetry circuit constant current input. asymmetry comparator voltage input. efm full-swing output. (low = v ss , high = v dd ) wide-band efm pll charge pump output. wide-band efm pll vco2 control voltage input. analog gnd. multiplier vco1 control voltage input. master pll (slave = digital pll) filter output. master pll filter input. master pll charge pump output. analog power supply. dc/dc converter output. leave open when not using. dc/dc converter output voltage monitor pin. connect to analog power supply when not using. analog gnd. dc/dc converter reset pin. d/a interface bit clock input. d/a interface serial data input. (2's comp, msb first) d/a interface lr clock input. d/a interface lr clock output. f = fs internal digital gnd. d/a interface serial data output. (2's comp, msb first) d/a interface bit clock output. internal digital power supply. high when the playback disc has emphasis, low it has not. high when de-emphasis is on, low when input off. power supply ? ? ? 1, 0 1, z, 0 ? analog 1, z, 0 ? ? ? 1, 0 ? 1, 0 1, 0 ? 1, 0 rfamp 3.3v asym 3.3v dc/dc 3.3v ? digital i/o = 3.3v internal = 2.5v
? 6 ? CXD3059AR pin no. symbol i/o description 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 iov dd 2 dout test tes1 iovss2 nc xv ss xtao xtai xv dd av dd 1 aout1 vrefl av ss 1 av ss 2 vrefr aout2 av dd 2 nc iov dd 0 rmut lmut nc xtsl iov ss 0 xtacn sqso sqck sbso exck xrst sysm d ata v ss xlat ? o i i ? ? ? o i ? ? o o ? ? o o ? ? ? o o ? i ? i o i o i i i i ? i i/o digital power supply. digital out output. test pin. normally gnd. test pin. normally gnd. i/o digital gnd. master clock gnd. crystal oscillation circuit output. crystal oscillation circuit input. master clock power supply. analog power supply. lch analog output. lch reference voltage. analog gnd. analog gnd. rch reference voltage. rch analog output. analog power supply. i/o digital power supply. rch "0" detection flag. lch "0" detection flag. crystal selection input. low when the crystal is 16.9344mhz; high when the crystal is 33.8688mhz. i/o digital gnd. oscillation circuit control. self-oscillation when high, oscillation stop when low. subcode q 80-bit and pcm peak and level data output. cd text data output. sqso readout clock input. subcode p to w serial output. sbso readout clock input. system reset. reset when low. mute input. muted when high. serial data input from cpu. internal digital gnd. latch input from cpu. the serial data is latched at the falling edge. power supply ? 1, 0 ? ? ? ? ? ? ? ? ? ? 1, 0 1, 0 ? ? 1, 0 1, 0 ? x'tal 2.5v digital i/o = 3.3v internal = 2.5v ? lch 3.3v rch 3.3v ? digital i/o = 3.3v internal = 2.5v
? 7 ? CXD3059AR pin no. symbol i/o description 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 clok v dd sens sclk atsk wfck xugf xpck gfs c2po scor v dd c4m wdck cout nc i ? o i i/o o o o o o o ? o o i/o ? serial data transfer clock input from cpu. internal digital power supply. sens output to cpu. sens serial data readout clock input. anti-shock input/output. wfck output. xugf output. output mnt0, rfck, sout by command switch. xpck output. output mnt1, sock by command switch. gfs output. output mnt2, xrof, xolt by command switch. c2po output. output mnt3, gtop by command switch. high output when the subcode sync, s0 or s1, is detected. internal digital power supply. 4.2336mhz output. 1/4 frequency-division output of the v16m in cav-w mode and variable pitch mode. word clock output. f = 2fs. grscor output by command switch. track number count signal input/output. power supply ? 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 ? 1, 0 1, 0 1, 0 ? digital i/o = 3.3v internal = 2.5v notes) pcmd is a msb first, two's complement output. gtop is used to monitor the frame sync protection status. (high: sync protection window released.) xugf is the frame sync obtained from the efm signal, and is negative pulse. it is the signal before sync protection. xpck is the inverse of the efm pll clock. the pll is designed so that the falling edge and the efm signal transition point coincide. the gfs signal goes high when the frame sync and the insertion protection timing match. rfck is derived from the crystal accuracy, and has a cycle of 136s. c2po represents the data error status. xrof is generated when the 32k ram exceeds the 28 frame jitter margin. c4m is a 4.2336mhz output that changes in cav-w mode and variable pitch mode. fsto is the 2/3 frequency-division output of the xtai pin. sout is the serial data output inside the servo block. sock is the serial data readout clock output inside the servo block. xolt is the serial data latch output inside the servo block.
? 8 ? CXD3059AR monitor pin output combinations command bit output data xugf mnt0 rfck c4m sout xpck mnt1 xpck gsto sock gfs mnt2 xrof gfs xolt c2po mnt3 gtop c2po c2po sro1 0 0 0 0 1 mtsl1 0 0 1 1 0 mtsl0 0 1 0 1 0 reset timing when power on power on with xrst pin low. set xrst pin high after holding it low 100ns or more to cancel reset.
? 9 ? CXD3059AR rf block pin equivalent circuit pin no. symbol i/o equivalent circuit description 19 vc 20 vc 21 22 1pf 23 24 1pf 25 19 e i tracking error amplifier input. 20 f i 21 tei i tracking error signal input to dssp block. 22 teo o tracking error amplifier output. 23 fei i focus error signal input to dssp block. 24 feo o focus error amplifier output. 25 vc i/o (av dd 4 ? av ss 4)/2 voltage output.
? 10 ? CXD3059AR pin no. symbol i/o equivalent circuit description rf summing amplifier and focus error amplifier input. 30 31 nc av dd 4 ? ? ? analog power supply. 32 rfdco i/o rfdc amplifier output. 33 pdsens i apc amplifier reference voltage (gnd signal) input. 26 27 28 29 15k ? 30k ? 30k ? 26 a i 27 b i 28 c i 29 d i ? ? 32 0.5pf 100 ? 10k ? 33 10k ? 59k ? 34 34 ac_sum o rfac summing amplifier output.
? 11 ? CXD3059AR pin no. symbol i/o equivalent circuit description equalizer circuit input. 36 ld o apc amplifier output. 37 pd i apc amplifier input. 35 vc 4k ? 4k ? 4k ? 4k ? 35 eq_in i 39 rfc i equalizer cut-off frequency adjustment. 36 500 ? 57k ? 10k ? 37 1k ? 38 nc ? ? ? 40 av ss 4 ? analog gnd. ? 41 vc 25 ? 41 rfaco o rfac amplifier output. 39
? 12 ? CXD3059AR electrical characteristics 1. dc characteristics (v dd = xv dd = 2.5 0.2v, iov dd 0 to 2 = av dd 0 to 5 = 3.3 0.3v, v ss = xv ss = iov ss = av ss = 0v, topr = ?20 to +75c) v v v v v v v a a a 0.7v dd 0.7v dd v ss v dd ? 0.4 v dd ? 0.4 v dd ? 0.4 v dd ? 0.4 ?10 40 ?10 schmitt input analog input i oh = ?2.4ma i ol = 4ma i oh = ?1.2ma i ol = 2ma i oh = ?2.4, ?4.8, ?7.2, ?9.6ma i ol = 4, 8, 12, 16ma i oh = ?0.28ma i ol = 0.36ma v in = v ss or v dd v in = v dd v in = v ss or v dd 0.5 100 0.2v dd 0.2v dd v dd 0.4 0.4 0.4 0.4 10 240 10 input voltage (1) input voltage (2) input voltage (3) output voltage (1) output voltage (2) output voltage (3) output voltage (4) input leak current input leak current (with pull-down resistor) tri-state output leak current (when high impedance) unit max. ty p. min. conditions item high level input voltage low level input voltage high level input voltage low level input voltage hysteresis input voltage high level output voltage low level output voltage high level output voltage low level output voltage high level output voltage low level output voltage high level output voltage low level output voltage ? 1, ? 3, ? 9 ? 2 ? 4, ? 12 ? 5, ? 8, ? 9 ? 6 ? 7 ? 11 ? 1, ? 2, ? 9 ? 3 ? 8 applicable pins v ih (1) v il (1) v ih (2) v il (2) vt + ? vt ? v in (3) v oh (1) v ol (1) v oh (2) v ol (2) v oh (3) v ol (3) v oh (4) v ol (4) i i i ih i oz
? 13 ? CXD3059AR applicable pins ? 1 pcmdi, emphi, test, tes1, xtsl, xtacn, sysm, data ? 2 bcki, lrcki, sqck, exck, xrst, xlat, clok, sclk ? 3 sstp ? 4 e, f, tei, fei, a, b, c, d, pdsens, eq_in, pd, rfc, rfaci, bias, asyi, vctl, cltv, fili, ddvrsen, ddcr ? 5 sfdr, srdr, tfdr, trdr, ffdr, frdr, lrck, pcmd, bck, emph, rmut, lmut, sqso, sbso, wfck, xugf, xpck, gfs, c2po, scor, c4m, wdck ? 6 asyo ? 7 dout ? 8 mdp, vpco, pco, sens ? 9 mirr, dfct, fok, lock, atsk, cout ? 10 teo, feo, ac_sum, ld, rfaco, ddvrout, aout1, vrefl, vrefr, aout2 ? 11 filo ? 12 vc, rfdco
? 14 ? CXD3059AR 2. ac characteristics (1) xtai pin (a) when using self-oscillation (v dd = xv dd = 2.5 0.2v, iov dd 0 to 2 = av dd 0 to 5 = 3.3 0.3v, v ss = xv ss = iov ss = av ss = 0v, topr = ?20 to +75c) oscillation frequency item f max symbol mhz unit (b) when inputting pulses to xtai pin (v dd = xv dd = 2.5 0.2v, iov dd 0 to 2 = av dd 0 to 5 = 3.3 0.3v, v ss = xv ss = iov ss = av ss = 0v, topr = ?20 to +75c) high level pulse width low level pulse width pulse cycle input high level input low level rise time, fall time item t whx t wlx t cx v ihx v ilx t r , t f symbol 6.6 6.6 14.6 1.7 0 min. typ. 32.7 32.7 59.5 0.7 10 max. ns ns ns v v ns unit t r t f t whx t wlx t cx v ilx v ihx 0.1 v ihx 0.9 v ihx xtai v dd /2 note) when the pulse is input to the xtai pin, be sure to input it via the capacitor. xtsl = l, $aexx1 cksl (1, 0) = 00 xtsl = h, $aexx1 cksl (1, 0) = 00 xtsl = h, $aexx1 cksl (1, 0) = 01 or 10 or 11 conditions 16.8 33.5 67.1 min. typ. 17.1 34.2 68.4 max. 16.9344 33.8688 67.7376
? 15 ? CXD3059AR (2) clok, data, xlat, sqck and exck pins (v dd = xv dd = 2.5 0.2v, iov dd 0 to 2 = av dd 0 to 5 = 3.3 0.3v, v ss = xv ss = iov ss = av ss = 0v, topr = ?20 to +75c) clock frequency clock pulse width setup time hold time delay time latch pulse width exck frequency exck pulse width sqck frequency sqck pulse width cout frequency (during input) ? cout pulse width (during input) ? item f ck t wck t su t h t d t wl f t t wt f t t wt f t f wt symbol 62.5 300 300 300 750 750 750 7.5 min. typ. 16 30000 30000 0.65 0.65 120000 65 max. mhz ns ns ns ns ns mhz ns mhz ns khz s unit ? only when $44 and $45 are executed. t wck t wck 1/f ck t h t su t wl t d 1/f t t wt t wt t h t su clok data xlat exck sqck cout sbso sqso t wsc
? 16 ? CXD3059AR (3) sclk pin t spw t dls 1/f sclk msb ... ... lsb xlat sclk serial read out data (sens) (v dd = xv dd = 2.5 0.2v, iov dd 0 to 2 = av dd 0 to 5 = 3.3 0.3v, v ss = xv ss = iov ss = av ss = 0v, topr = ?20 to +75c) sclk frequency sclk pulse width delay time item f sclk t spw t dls symbol 16 min. typ. max. mhz ns s unit 31.3 15 (4) cout, mirr and dfct pins operating frequency (v dd = xv dd = 2.5 0.2v, iov dd 0 to 2 = av dd 0 to 5 = 3.3 0.3v, v ss = xv ss = iov ss = av ss = 0v, topr = ?20 to +75c) cout maximum operation frequency mirr maximum operation frequency dfct maximum operation frequency item f cout f mirr f dfcth symbol 40 40 5 min. typ. max. khz khz khz unit ? 1 ? 2 ? 3 conditions ? 1 when using a high-speed traverse tzc ? 2 when the rf signal continuously satisfies the following conditions during the traverse. a = 0.11v dd to 0.23v dd 25% ? 3 during complete rf signal omission. when settings related to dfct signal generation are typ. a b b a + b
? 17 ? CXD3059AR 1-bit dac and lpf block analog characteristics (v dd = xv dd = 2.5v, iov dd 0 to 2 = av dd 0 to 5 = 3.3v, v ss = xv ss = iov ss = av ss = 0v, topr = +25c) total harmonic distortion signal-to-noise ratio item % db unit thd s/n symbol 1khz sine wave, 0db data, 20khz lpf 1khz sine wave, 0db data, amut off (using a-weighting filter 20khz lpf) conditions fs = 44.1khz in all cases. the total harmonic distortion and signal-to-noise ratio measurement circuits are shown below. 22f aout1 (2) vrefl (r) 1f 100 ? 2200pf 100k ? audio analyzer lpf external circuit diagram audio analyzer CXD3059AR rch a lch b data r f test disc block diagram of analog characteristics measurement (v dd = xv dd = 2.5v, iov dd 0 to 2 = av dd 0 to 5 = 3.3v, v ss = xv ss = iov ss = av ss = 0v, topr = +25c) output voltage load resistance vref pin capacitance item v out r l c vref symbol 920 10 min. typ. max. mvrms k ? f unit ? 1 ? 1 ? 2 applicable pins 928 1 ? measurement is conducted for the above circuit diagrams with the sine wave output of 1khz and 0db. applicable pins ? 1 aout1, aout2 ? 2 vrefl, vrefr 0.014 min. typ. max. 90 0.006 95
? 18 ? CXD3059AR rf block electrical characteristics (v dd = xv dd = 2.5v, iov dd 0 to 2 = av dd 0 to 5 = 3.3v, v ss = xv ss = iov ss = av ss = 0v, topr = +25c) measurement item input impedance (a, b, c and d) input impedance (e and f) input impedance (pd) rf block current consumption (on operation) rf block current consumption (on standby) output voltage input voltage output voltage (on standby) input voltage range maximum output current output impedance symbol r a,b,c,d r e,f r pd i avd i stb v vc v pd v ld stb v pdt v pdb i ld r ld sw conditions connect to vc except measure- ment pins. sending command $3af100 $adf7cc00 $ad000800 ac input amplitude ac input frequency dc input voltage v pd + 12mv v pd ? 12mv 0 v pd dc input current 3ma 0 0 0 0 1ma 1ma bias conditions v dd 2.5v 2.5v 2.5v 2.5v av dd 3.3v 3.3v 3.3v 3.3v measurement conditions pin current pin current pin current pin current pin current pin voltage p d input voltage which ld pin voltage is 1.41v pin voltage pin voltage pin voltage pin voltage pin voltage measure- ment pins a, b, c, d e, f pd av dd 4 av dd 4 vc ld, pd ld ld ld ld ld apc vc min. 10 21 10 0.5av dd ? 0.1 100 av dd ? 0.2 1.89 0.43 0.34 1.66 ty p. 15 30 40 0.5av dd 150 2.14 0.68 0.64 1.91 max. 20 39 70 1 0.5av dd + 0.1 200 2.39 0.93 0.94 2.16 unit k ? k ? m ? ma ma v mv v v v v v
? 19 ? CXD3059AR measurement item input voltage range output voltage range input conversion dc offset voltage input conversion dc offset temperature drift offset voltage frequency characteristics 1 frequency characteristics 2 distortion rate input voltage range output voltage range input conversion dc offset voltage input conversion dc offset temperature drift frequency characteristics 1 frequency characteristics 2 distortion rate symbol v ir-acsum v or-acsum v of-acsum v df-acsum v offsum f sum1 f sum2 d sum v ir-rfdc v or-rfdc v of-rfdc v df-rfdc f rfdc1 f rfdc2 d rfdc sw conditions sending command $3aa000 $3aa01c $3aa004 $3aa018 $3aa000 $3aa01c $3aa004 $3aa018 ac input amplitude ac input frequency dc input voltage dc input current vc + vac1/2 vc + vac1/2 vc + vac1/2 bias conditions v dd 2.5v 2.5v av dd 3v 3v measurement conditions pin voltage, a + b + c + d pin voltage pin voltage pin voltage 20 log (v6m/v0.2m) (v6m/v3m) 100 pin voltage, a + b + c + d pin voltage pin voltage 20 log (v6m/v0.2m) measure- ment pins rfdc rfdc rfdc rfdc rfdc rfdc rfdc rfdc rfdc rfdc rfdc 61mvp-p 104mvp-p 600mvp-p 61mvp-p 104mvp-p 1.5vp-p 0.2/6mhz 3mhz 0.2/6mhz 100khz acsum rfdc min. 0.5av dd ? 0.1 0.47av dd 0.5av dd ? 0.23 0.7 ?4 ?4 0.3av dd ? 0.1 0.25av dd 0.3av dd ? 0.23 ?4 ?4 ty p. 6 0.9 0 0 6 0 0 0.1 max. 0.9av dd + 0.1 0.65av dd 0.5av dd + 0.23 1.1 1 1 3 0.7av dd + 0.1 0.75av dd 0.3av dd + 0.23 1 1 unit v v v v/ c v db db % v v v v/ c db db %
? 20 ? CXD3059AR measurement item input voltage range output voltage range input conversion dc offset voltage input conversion dc offset temperature drift offset voltage frequency characteristics 1 frequency characteristics 2 distortion rate input voltage range output voltage range input conversion dc offset voltage input conversion dc offset temperature drift offset voltage frequency characteristics 1 frequency characteristics 2 distortion rate symbol v ir-fe v or-fe v of-fe v df-fe v offfe f fe1 f fe2 d fe v ir-te v or-te v of-te v df-te v offte f te1 f te2 d te sw conditions sending command $3aa104 $3aa118 $3aa204 $3aa218 $3aa200 ac input amplitude ac input frequency dc input voltage dc input current bias conditions v dd 2.5v 2.5v av dd 3v 3v measurement conditions vc reference about (b + d) and (a + c) pin voltage pin voltage pin voltage 20 log (v100k/v10k) (v50k/v100k) 100 vc reference about (b + d) and (a + c) pin voltage pin voltage pin voltage 20 log (v100k/v10k) (v50k/v100k) 100 measure- ment pins fe fe fe fe fe fe te te te te te te 30mvp-p 52mvp-p 600mvp-p 28mvp-p 45mvp-p 480mvp-p 10/ 100khz 50khz 10/ 100khz 50khz fe te min. 0.375 av dd 0.5 0.5av dd ? 0.03 ?0.06 ?1 ?1 0.4av dd 0.5 0.5av dd ? 0.03 ?0.075 ?1 ?1 ty p. 2.8 0 0 0 2.5 0 0 0 max. 0.625 av dd av dd ? 0.5 0.5av dd + 0.03 0.06 1 1 3 0.6av dd av dd ? 0.5 0.5av dd + 0.03 0.075 1 1 3 unit v v v v/ c v db db % v v v v/ c v db db %
? 21 ? CXD3059AR measurement item input voltage range output voltage range input conversion dc offset voltage input conversion dc offset temperature drift offset voltage frequency characteristics 1 frequency characteristics 2 distortion rate symbol v ir-eq v or-eq v of-eq v df-eq v offeq f eq1 f eq2 d eq sw conditions sending command $3aa204 $3aa218 $3aa200 ac input amplitude ac input frequency dc input voltage dc input current bias conditions v dd 2.5v av dd 3v measurement conditions distortion rate 3% or less, no dc bias pin voltage pin voltage ta = ?20 to +75c pin voltage 20 log (v100k/v10k) (v720k/v360k) 100 measure- ment pins rfaco rfaco rfaco rfaco rfaco rfaco 28mvp-p 45mvp-p 1.2vp-p 10/ 100khz 360khz eq min. 0.5 ?0.25 ?0.5 ?1 ?1 ty p. 0.1 0 0 0 max. 250 av dd ? 0.5 0.25 0.5 1 1 3 unit mvp-p v v v v db db %
? 22 ? CXD3059AR notes on operation for rfc pin set each impedance of the heavy line shown bellow 0.1 ? or less. make each wiring length of l1 to l4, l1 20mm, l2 20mm and l3 + l4 40mm. use the bypass condenser c with capacitance led by resistance (regulator output impedance and wiring resistance to c) or more seeing the figure bellow. regulator gnd out 15k ? 0.1f l2 l3 l1 av ss 4 rfc av dd 4 l4 r avs c 0.1f 5 4 3 2 1 0 0204060 c [f] r [ ? ] 80 100 impedance r tolerance for bypass condenser c
? 23 ? CXD3059AR dc-dc converter characteristics (v dd = xv dd = 2.5 0.2v, iov dd 0 to 2 = av dd 0 to 5 = 3.3 0.3v, v ss = xv ss = iov ss = av ss = 0v, topr = ?20 to +75c) dc-dc converter application circuit sample (1) c 2 is the oscillation stopping capacitor. since there is possibility of an oscillation when the capacity value changes by temperature change etc., the electrolytic capacitor with small internal series resistance (esr) is recommended. capacitance 100f is recommended. (should be 50f or more) (2) since protection circuit is built in the dc-dc converter output, it operates when an overcurrent flows. cancelling after protection circuit operation needs to make power supply voltage 0.7v or less once. after that, when you switch on power supply, set xrst pin in the condition of low. to cancel the reset, set high after holding xrst low 100ns or more after power on. (3) the r 1 and c 1 of application circuit example have the constant assuming that power supply rise time is 400ms or less. when it is 400ms or more, it is necessary to enlarge the value of r 1 c 1 . c 1 r 1 ddvrout ddcr c 2 vout output voltage output current item 2.7 100 min. typ. max. v ma unit 2.3 ? v o iope symbol 2.5 ? ? ? conditions
? 24 ? CXD3059AR cpu interface timing spindle output servo output 750ns to 30s d18 d19 d20 d21 d22 d23 750ns or more valid clok data xlat registers d0 d1 64t mck 64t mck 64t mck at mck at mck sfdr srdr sld 32t mck 32t mck 32t mck 32t mck 32t mck 32t mck fcs/trk ffdr/ tfdr frdr/ trdr output value + a output value ? a output value 0 t mck a 2 t mck a 2 t mck a 2 t mck a 2 mck (5.6448mhz) mdp acceleration z deceleration 132khz 7.6s n . 236 (ns) n = 0 to 31 mdp acceleration z deceleration 264khz 3.8s
? 25 ? CXD3059AR da interface cddsp output selected (1 speed playback lrck = 44.1khz, bck = 2.1168mhz) dac output selected (1 speed playback lrck = 44.1khz, bck = 2.8224mhz) $a5ea obit1 = 1, obit0 = 1 dac block input timing (lrck = 44.1khz, bck = 2.1168mhz) $a5ea obit1 = 1, obit0 = 0 $a5ea obit1 = 0, obit0 = 0 lrck wdck bck 1 24 pcmd r0 lch msb (15) l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 rch msb 23456789101112 lrck wdck bck 1 32 pcmd r0 lch msb (15) l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 rch msb pcmd r0 lch msb (17) l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 rch msb pcmd r0 lch msb (19) l14 l13 l12 l11 l16 l15 l18 l17 l16 l15 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 rch msb 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 lrcki bcki 1 24 pcmdi r0 lch msb (15) l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 rch msb 23456789101112
? 26 ? CXD3059AR application circuit ddvrout lrck pcmd bck rfdco mirr dfct lock cout wdck c4m c2po gfs xpck xugf wfck sbso lmut emph dout lch rch rmut driver circuit limit switch pd ld a.gnd d c b a vc f e fd td driver circuit sled spdl sqso sqck xrst sysm data xlat clok sens sclk scor fok CXD3059AR 36 35 34 31 32 33 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 40 39 38 37 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 97 96 95 94 91 92 93 99 98 73 74 81 82 83 84 75 76 77 78 88 87 86 85 79 80 89 90 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 rmut iov dd 0 nc av dd 2 aout2 vrefr av ss 2 av ss 1 vrefl aout1 av dd 1 xv dd xtai xtao xv ss nc iov ss 2 tes1 test dout iov dd 2 emphi emph v dd bck pcmd v ss lrck lrcki pcmdi lmut bcki nc nc xtsl ddcr iov ss 0 av ss 5 xtacn ddvrsen sqso ddvrout sqck av dd 5 sbso pco exck fili xrst filo sysm cltv data av ss 3 v ss vctl xlat vpco clok asyo v dd asyi sens bias sclk av dd 3 atsk rfaci wfck rfaco xugf av ss 4 xpck rfc gfs nc c2po pd scor ld v dd eq_in c4m ac_sum wdck pdsens cout rfdco nc av dd 4 mirr dfct fok v ss lock mdp sstp iov ss 1 sfdr srdr tfdr trdr ffdr frdr iov dd 1 av dd 0 av ss 0 nc e f tei teo fei feo vc a b c d nc application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 27 ? CXD3059AR package outline unit: mm sony corporation sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin palladium plating copper alloy 0.5 b m 0.1 detail a detail b b = 0.20 0.03 0.125 0.03 1.7 max 1.4 0.1 b a 120pin lqfp (plastic) lqfp-120p-l01 lqfp120-p-1616 0.8g 130 31 60 61 90 91 120 0.1 s s s 18.0 0.2 16.0 0.1 (17.0) (0.5) 0? to 10? 0.1 0.05 0.6 0.15 0.25

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